Highlights: - Productive: Designed for maximum engineering productivity and time-to-market acceleration for connecting semiconductor IP blocks and sub-systems for Arm and RISC-V-based designs, accelerating time to results. - Configurable: Scales across a mix of fully coherent, IO-coherent, non-coherent, memory and peripheral interfaces using a variety of NoC topologies, delivering best-in-class architectural flexibility. - Functionally Safe: Ready to meet ISO 26262 requirements from ASIL B to ASIL D for aut ...